kaz29Вестник Казахстанско-Британского технического университетаHerald of the Kazakh-British Technical University1998-66882959-8109Казахстанско-Британский Технический Университет10.55452/1998-6688-2026-23-3-188-203kaz29-3185Research ArticleКОМПЬЮТЕРНЫЕ НАУКИCOMPUTER SCIENCEАРХИТЕКТУРА ЦЕЛОЧИСЛЕННОГО ДЕЛИТЕЛЯ С ОДНОВРЕМЕННЫМ ФОРМИРОВАНИЕМ ТРЕХ РАЗРЯДОВ ЧАСТНОГО ЗА ШАГA SEQUENTIAL INTEGER DIVIDER WITH THREE-BIT QUOTIENT DIGIT GENERATIONhttps://orcid.org/0000-0002-9326-9476ТынымбаевС.TynymbayevS.

Профессор

Алматы

Professor

Almaty

s.tynymbayev@iitu.edu.kzhttps://orcid.org/0009-0001-7277-5492МамановаС. Е.MamanovaS. E.

Докторант

Алматы

PhD Candidate

Almaty

s.mamanova@iitu.edu.kzhttps://orcid.org/0000-0002-5196-8252СқабыловА. А.SkabylovA. A.

PhD

Алматы

PhD

Almaty

Alisher.skabylov@kaznu.edu.kzhttps://orcid.org/0000-0002-2657-3697ЧинибаеваТ. Т.ChinibayevaT. T.

PhD

Алматы

PhD

Almaty

t.temirbolatova@iitu.edu.kzhttps://orcid.org/0009-0008-1884-4662ЖексебайД. М.ZhexebayD. M.

PhD

Алматы

PhD

Almaty

zhexebay92@gmail.comМеждународный университет информационных технологийКазахстанInternational Information Technology UniversityKazakhstanКазахский национальный университет им. аль-ФарабиКазахстанAl-Farabi Kazakh National UniversityKazakhstan202625092026233188203Copyright © Тынымбаев С., Маманова С.Е., Сқабылов А.А., Чинибаева Т.Т., Жексебай Д.М., 20262026Тынымбаев С., Маманова С.Е., Сқабылов А.А., Чинибаева Т.Т., Жексебай Д.М.Tynymbayev S., Mamanova S.E., Skabylov A.A., Chinibayeva T.T., Zhexebay D.M.Данная работа распространяется под лицензией Creative Commons Attribution 4.0.This work is licensed under a Creative Commons Attribution 4.0 License.https://vestnik.kbtu.edu.kz/jour/article/view/3185

Операция целочисленного деления является одной из наиболее ресурсоёмких арифметических опера­ций в цифровых вычислительных системах. Традиционные последовательные делители формируют один разряд частного за такт, что требует n тактов для n-разрядного деления. В данной работе предлагается ар­хитектура последовательного целочисленного делителя, обеспечивающая одновременное формирование трех разрядов частного за один тактовый цикл (что соответствует основанию radix-8). Устройство включает регистр делимого (РгА), формирователь кратных делителю (БФКД), формирователь частичных остатков и разрядов частного (ФЧОиРЧ) и блок синхронизации (БС). В отличие от классических SRT-делителей с избыточным представлением и таблицами выбора цифры частного, предложенная архитектура использует точное сравнение частичного остатка с предвычисленными кратными делителю B-7B, что устраняет рост таблицы выбора при увеличении основания. Архитектура описана на языке Verilog HDL и верифицирова­на на ПЛИС Xilinx Artix-7 в среде Vivado. Прототип для 12-разрядного делимого и 6-разрядного делителя занимает 158 LUT и 50 триггеров, достигает максимальной тактовой частоты 134,6 МГц и подтвержден комплексом из десяти тестов; деление выполняется за два тактовых цикла. Архитектура ориентирована на применение в высокоскоростных цифровых вычислителях и специализированных процессорах.

Integer division remains one of the most computationally demanding arithmetic operations in digital computing systems. Conventional sequential dividers produce one quotient bit per clock cycle, requiring n cycles for an n-bit division. This paper proposes an architecture for a sequential integer divider capable of simultaneously generating three quotient bits per clock cycle. The proposed device comprises a dividend register (DR), a divisor multiples generator (DMG), a partial remainder and quotient digit generator (PRQDG), and a synchronization unit (SU). Unlike classical SRT dividers, which rely on a redundant quotient representation and quotient-digit selection tables, the proposed architecture performs an exact comparison of the partial remainder against the precomputed divisor multiples B-7B, thereby eliminating the growth of the selection table as the radix increases. The architecture is described in Verilog HDL and verified on a Xilinx Artix-7 FPGA using the Vivado design suite. The prototype for a 12-bit dividend and a 6-bit divisor occupies 158 LUTs and 50 flip-flops, attains a maximum clock frequency of 134.6 MHz, and is confirmed by a suite of ten tests; a division is completed in two clock cycles. The architecture is intended for use in high-speed digital computing units and specialized processors.

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The authors declare that there are no conflicts of interest present.